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NXP Semiconductors
LPC1111/12/13/14
4 GB
LPC1111/12/13/14
0xFFFF FFFF
AHB peripherals
0x5020 0000
127- 4 reserved
reserved
0x5004 0000
3
GPIO PIO3
0x5003 0000
AHB peripherals
0x5020 0000
0x5000 0000
2
1
GPIO PIO2
GPIO PIO1
0x5002 0000
0x5001 0000
reserved
0
GPIO PIO0
APB peripherals
23 - 31 reserved
0x5000 0000
0x4008 0000
1 GB
APB peripherals
0x4008 0000
0x4000 0000
22
SPI1 (1)
0x4005 C000
0x4005 8000
21 - 19 reserved
0x4004 C000
18
system control
0x4004 8000
reserved
17
16
IOCONFIG
SPI0
0x4004 4000
0x4004 0000
0.5 GB
0x2000 0000
15
14
reserved
PMU
0x4003 C000
0x4003 8000
reserved
0x1FFF 4000
10 - 13 reserved
0x4002 8000
16 kB boot ROM
0x1FFF 0000
9
reserved
0x4002 4000
reserved
0x1000 2000
8
7
reserved
ADC
0x4002 0000
0x4001 C000
8 kB SRAM (LPC1113/14/301)
4 kB SRAM (LPC1111/12/13/14/201)
2 kB SRAM (LPC1111/12/101)
0x1000 1000
0x1000 0800
0x1000 0000
6
5
4
3
32-bit counter/timer 1
32-bit counter/timer 0
16-bit counter/timer 1
16-bit counter/timer 0
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0 GB
reserved
32 kB on-chip flash (LPC1114)
24 kB on-chip flash (LPC1113)
16 kB on-chip flash (LPC1112)
8 kB on-chip flash (LPC1111)
0x0000 8000
0x0000 6000
0x0000 4000
0x0000 2000
0x0000 0000
2
1
0
+ 512 byte
active interrupt vectors
UART
WDT
I 2 C-bus
0x0000 0200
0x0000 0000
0x4000 8000
0x4000 4000
0x4000 0000
002aae699
(1) LQFP48/PLCC44 packages only.
Fig 5.
LPC1111/12/13/14 memory map
7.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.5.1 Features
? Controls system exceptions and peripheral interrupts.
LPC1111_12_13_14_0
? NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 00.11 — 13 November 2009
19 of 53
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